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CS8120 5.0 V, 300 mA Linear Regulator with RESET and ENABLE
The CS8120 is a 5.0 V, 300 mA precision linear regulator with two microprocessor compatible control functions and protection circuitry included on chip. The composite NPN-PNP output pass transistor assures a lower dropout voltage (1.0 V @ 200 mA) without requiring excessive supply current (2.5 mA). The CS8120's two logic control functions make this regulator well suited to applications requiring microprocessor-based control at the board or module level. ENABLE controls the output stage. A high voltage (> 2.9 V) on the ENABLE lead turns off the regulator's pass transistor and sends the IC into Sleep mode where it draws only 250 mA. The RESET function sends a RESET signal when the IC is powering up or whenever the output voltage moves out of regulation. The RESET signal is valid down to VOUT = 1.0 V. The CS8120 design optimizes supply rejection by switching the internal bandgap reference from the supply input to the regulator output as soon as the nominal output voltage is achieved. Additional on chip filtering enhances rejection of high frequency transients on all external leads. The CS8120 is fault protected against short circuit, over voltage and thermal runaway conditions.
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TO-220-5 T SUFFIX CASE 314D
1 5 TO-220-5 TVA SUFFIX CASE 314K
1
TO-220-5 THA SUFFIX CASE 314A 1 5 D2PAK-5 DP SUFFIX CASE 936AC 1 5 DIP-8 N SUFFIX CASE 626 8 1 SO-14 D SUFFIX CASE 751A 1
* * * * * *
5.0 V 4.0% Output Voltage 300 mA Low Dropout Voltage (1.0 V @ 150 mA) Low Quiescent Current (2.5 mA @ IOUT = 150 mA) mP Compatible Control Functions - RESET - ENABLE Low Current Sleep Mode - IQ = 250 mA Fault Protection - Thermal Shutdown - Short Circuit - 60 V Load Dump
14
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 10 of this data sheet.
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 10 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2004
1
January, 2004 - Rev. 8
Publication Order Number: CS8120/D
CS8120
PIN CONNECTIONS
TO-220-5 VOUT Tab = GND Pin 1. VIN 2. ENABLE 3. GND 4. RESET 5. VOUT 1 VIN NC ENABLE 1 DIP-8 8 GND SENSE RESET NC Pin 1. VIN 2. ENABLE 3. GND 4. RESET 5. VOUT 1 D2PAK-5 VIN NC NC NC ENABLE NC NC 1 SO-14 14 VOUT GND SENSE NC RESET NC NC
VOUT VIN Over Voltage Shutdown
Output Current Limit - + Error Amplifier
ENABLE
- +
ENABLE Comparator Bandgap Supply
VREF
Thermal Protection
To VOUT
Bandgap Reference Reset Comparator + - GND
RESET
Figure 1. Block Diagram - TO-220-5 ABSOLUTE MAXIMUM RATINGS*
Rating DC Input Voltage Load Dump Output Current Electrostatic Discharge (Human Body Model) Operating Temperature Junction Temperature Storage Temperature Range Lead Temperature Soldering: 1. 10 second maximum. 2. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Value -0.7 to 26 60 Internally Limited 2.0 -40 to +125 -40 to +150 -55 to +150 260 peak 230 peak Unit V V - kV C C C C C
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CS8120
ELECTRICAL CHARACTERISTICS (VIN = 14 V, IOUT = 5.0 mA; -40 TJ 150C, -40C TC 125C,
unless otherwise noted.) Note 3 Characteristic Output Stage Output Voltage, VOUT Line Regulation Load Regulation Supply Voltage Rejection Dropout Voltage Quiescent Current Protection Circuits Short Circuit Current Thermal Shutdown Overvoltage Shutdown RESET RESET Saturation Voltage RESET Output Leakage Current Power ON/OFF RESET Peak Output Voltage RESET Threshold HIGH (VRH) LOW (VRL) RESET Threshold Hysteresis ENABLE Input High Voltage Input Low Voltage Input Hysteresis Input Current 7.0 V < VIN < 26 V 7.0 V < VIN < 26 V 7.0 V < VIN < 26 V GND < VIN(HI) < VOUT - 1.1 0.4 -10 2.9 2.1 0.8 0 3.9 - 2.8 +10 V V V mA 1.0 V < VOUT < VRT(OFF), 3.1 kW Pull-Up to VOUT ENABLE = Low, VOUT > VRT(ON), VRESET = VOUT 3.1 kW Pull-Up to VOUT - - - 0.1 0 0.7 0.4 25 1.0 V mA V - - - 300 150 26 600 190 40 - - - mA C V 7.0 V VIN 26 V, 1.0 mA IOUT 300 mA 7.0 V VIN 26 V, IOUT = 200 mA 1.0 mA IOUT 300 mA VIN = 14 VDC + 1.0 VRMS @ 120Hz LOAD = 25 W IOUT = 200 mA ENABLE = High, VIN = 12 V ENABLE = Low, IOUT = 200 mA 4.8 - - 40 - - - 5.0 - - 70 1.0 0.25 2.5 5.2 50 50 - 1.5 0.65 15 V mV mV dB V mA mA Test Conditions Min Typ Max Unit
VOUT Increasing VOUT Decreasing -
- 4.75 10
VOUT - 0.10 VOUT - 0.14 40
VOUT - 0.04 - -
V V mV
3. To have safe operating junction temperatures, low duty cycle pulse testing is used on tests where applicable.
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CS8120
PACKAGE LEAD DESCRIPTION
PACKAGE LEAD # TO-220-5 1 2 3 4 DIP-8 2 4 8 6 SO-14 1 5 13 10 D2PAK-5 1 2 3 4 LEAD SYMBOL VIN ENABLE GND RESET FUNCTION Supply voltage to IC, usually direct from the battery. CMOS compatible logical input. VOUT is disabled i.e. placed in a high impedance state when ENABLE is high. Ground Connection. CMOS compatible output lead. RESET goes low whenever VOUT falls out of regulation. The RESET delay is externally programmed. Regulated output voltage, 5.0 V (Typ). Kelvin Connection which allows remote sensing of output voltage for improved regulation. If remote sensing is not desired, connect to VOUT. No Connection.
5 N/A
1 7
14 12
5 -
VOUT SENSE
-
3, 5
2, 3, 4, 6, 7, 8, 9, 11
NC
TYPICAL PERFORMANCE CHARACTERISTICS
5.02 5.01
5.0 V @ 25C
0
IOUT = 100 mA
-5 -10 Load Reg. (mV) -15 -20 -25 -30 -35 -40
VIN = 14 V 125C
40C 25C
5.0 VOUT (V) 4.99 4.98 4.97 4.96 4.95
-40 -20 0 20 40 60 80 100 120 140 150
-45 -50
0 100 200 300 400 500
Junction Temperature (C)
IOUT (mA)
Figure 2. Output Voltage vs. Temperature
Figure 3. Load Regulation vs. Output Current Over Temperature
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CS8120
TYPICAL PERFORMANCE CHARACTERISTICS
50
VIN = 7 to 25 V
1.4 1.2 1.0 0.8
25C -40C
40 30 20
125C
25C
Dropout Voltage. (V)
Line Reg. (mV)
0.6 0.4 0.2
125C
10
-40C
0 -10
0 50 100 150 200 250 300 350 400 450 500
0.0
0
50
100
150
200
250
300
350
IOUT (mA)
Output Current (mA)
Figure 4. Line Regulation vs. Output Current Over Temperature
3.5
VIN = 14 V
Figure 5. Dropout Voltage vs. Output Current Over Temperature
5.5 5 22 20
VOUT
3.0 Quiescent Current (mA)
-40C 25C
2.0
125C
3 2
IQ
12 8 4 0
1.5 1.0
1 0.5 0.0 0
0 50 100 150 200 250 300 350 0 2 4 6 8 10
Output Current (mA)
Supply Voltage (V)
Figure 6. Quiescent Current vs. Output Current Over Temperature
2000 1800 Reset Output Voltage (mV) 1600 1400 1200 1000 800 600 400 200 0
1 5 10 15 20 25 VIN = 5.0 V
Figure 7. Output Voltage and Supply Current vs. Input Voltage
30
35
40
Reset Output Current (mA)
Figure 8. RESET Output Voltage vs. Output Voltage
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Supply Current (mA)
2.5
4 VOUT (V)
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CS8120
CIRCUIT DESCRIPTION
VOLTAGE REFERENCE AND OUTPUT CIRCUITRY Precision Voltage Reference
The regulated output voltage depends on the precision band gap voltage reference in the IC. By adding an error amplifier into the feedback loop, the output voltage is maintained within 4.0% over temperature and supply variation.
Output Stage
The composite PNP-NPN output structure (Figure 9) provides 300 mA (Typ) of output current while maintaining a low drop out voltage (1.00 V, Typ) and drawing little quiescent current (2.5 mA). The NPN pass device prevents deep saturation of the output stage which in turn improves the IC's efficiency by preventing excess current from being used and dissipated by the IC.
VIN
circuitry and enables the IC to survive unexpected voltage transients. Using an emitter sense scheme, the amount of current through the NPN pass transistor is monitored. Feedback circuitry insures that the output current never exceeds a preset limit. Should the junction temperature of the power device exceed 180C (Typ) the power transistor is turned off. Thermal shutdown is an effective means to prevent die overheating since the power transistor is the principle heat source in the IC.
REGULATOR CONTROL FUNCTIONS
The CS8120 contains two microprocessor compatible control functions: ENABLE and RESET (Figure 11).
ENABLE Function
The ENABLE function switches the output transistor. When the voltage on the ENABLE lead exceeds 2.9 V Typ, the output pass transistor turns off, leaving a high impedance facing the load. The IC will remain in Sleep mode, drawing only 250 mA, until the voltage on the lead drops below 2.1 V Typ. Hysteresis (800 mV) is built into the ENABLE function to provide good noise immunity.
For 7.0 V < VIN < 26 V
VOUT
VIN ENABLE VIN(H) VRH VOUT VRL (1) VRPEAK RESET VRLO (1) = No Reset Delay Capacitor (2) = With Reset Delay Capacitor (2) VRPEAK
Figure 9. Composite Output Stage of the CS8120 Output Stage Protection
The output stage is protected against overvoltage, short circuit and thermal runaway conditions (Figure 10).
> 26 V VIN VOUT
Figure 11. Circuit Waveform for CS8120
IOUT
RESET Function
Load Dump Short Circuit Thermal Shutdown
Figure 10. Typical Circuit Waveforms for Output Stage Protection
If the input voltage rises above 26 V (e.g. load dump), the output shuts down. This response protects the internal
A RESET signal (low voltage) is generated as the IC powers up (VOUT > VOUT - 100 mV) or when VOUT drops out of regulation (VOUT < VOUT - 140 mV, Typ). 40 mV of hysteresis is included in the function to minimize oscillations. The RESET output is an open collector NPN transistor, controlled by a low voltage detection circuit. The circuit is
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CS8120
functionally independent of the rest of the IC, thereby guaranteeing that the RESET signal is valid for VOUT as low as 1.0 V.
VOUT 5.0 V to mP and System Power RRST C2 22 mF to mP RESET Port CRST
An external RC network on the RESET lead (Figure 12) provides a sufficiently long delay for most microprocessor based applications. RC values can be chosen using the following formula:
RTOT CRST + -tDelay ln
VT*VOUT VRST*VOUT
CS8120
RESET
Figure 12. RC Network for RESET Delay Circuitry
where: RTOT = RRST in parallel with RIN, RIN = mP port impedance, CRST = RESET delay capacitor, tDelay = desired delay time, VRST = VSAT of RESET lead (0.7 V @ turn - ON), and VT = mP logic threshold voltage.
APPLICATION NOTES The circuit depicted in Figure 13 lets the microprocessor control its power source, the CS8120 regulator. An I/O port on the mP and the SWITCH port are used to drive the base of Q1. When Q1 is driven into saturation, the voltage on the ENABLE lead falls below its lower threshold. The regulator's output is switched out. When the drive current is removed, the voltage on the ENABLE lead rises, the output is switched off and the IC moves into Sleep mode where it draws 250 mA. By coupling these two controls with the ENABLE, the system has added flexibility. Once the system is running, the state of the SWITCH is irrelevant as long as the I/O port continues to drive Q1. The microprocessor can turn off its own power by withdrawing drive current, once the SWITCH is open. This software control at the I/O port allows the microprocessor to finish key housekeeping functions before power is removed. The logic options are summarized in Table 1.
Table 1. Logic Control of CS8120 Output
Microprocessor I/O Drive ON SWITCH Closed Open OFF Closed Open ENABLE LOW LOW LOW HIGH Output ON ON ON OFF
The I/O port of the microprocessor typically provides 50 mA to Q1. In automotive applications the SWITCH is connected to the ignition switch.
VBAT C1 0.1 mF 500 kW
VIN
VOUT
VCC C2 22mF mP
CS8120
ENABLE RESET
RRST
GND
RESET CRST I/O Port
Q1 100 kW 500 kW SWITCH 100 kW
Figure 13. Microprocessor Control of CS8120 Using External Switching Transistor Q1
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CS8120
STABILITY CONSIDERATIONS
The output or compensation capacitor, C2, helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instability. The aluminum electrolytic capacitor is the least expensive solution, but, if the circuit operates at low temperatures (-25C to -40C), both the value and ESR of the capacitor will vary considerably. The capacitor manufacturers data sheet usually provides this information. The value for the output capacitor C2 shown in Figure 14 should work for most applications, however it is not necessarily the optimized solution.
5.0 V to mP and System Power VOUT CS8120 RESET ENABLE RRST to mP RESET port CRST C2** 10 mF
the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage conditions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above.
CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR
VIN C1 * 0.1 mF
*C1 is required if regulator is far from the power source filter. **C2 is required for stability.
Figure 14. Circuit Showing Output Compensation Capacitor
The maximum power dissipation for a single output regulator (Figure 15) is:
PD(max) + VIN(max) * VOUT(min) IOUT(max) ) VIN(max)IQ
To determine an acceptable value for C2 for a particular application, start with a tantalum capacitor of the recommended value and work towards a less expensive alternative part. Step 1: Place the completed circuit with a tantalum capacitor of the recommended value in an environmental chamber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscillations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause
(1)
where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permissible value of RqJA can be calculated:
RQJA + 150C * TA PD
(2)
The value of RqJA can then be compared with those in the package section of the data sheet. Those packages with RqJA's less than the calculated value in equation 2 will keep the die temperature below 150C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required.
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CS8120
IIN VIN IOUT
HEAT SINKS
VOUT
SMART REGULATOR(R)
Control Features
IQ
A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of RqJA.
RQJA + RQJC ) RQCS ) RQSA
(3)
Figure 15. Single Output Regulator With Key Performance Parameters Labeled
where: RqJC = the junction-to-case thermal resistance, RqCS = the case-to-heatsink thermal resistance, and RqSA = the heatsink-to-ambient thermal resistance. RqJC appears in the package section of the data sheet. Like RqJA, it too is a function of package type. RqCS and RqSA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
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CS8120
ORDERING INFORMATION Device CS8120YT5 CS8120YTVA5 CS8120YTHA5 CS8120YN8 CS8120YDP5 CS8120YDPR5 CS8120YD14 CS8120YDR14 Description TO-220-5 TO-220-5 TO-220-5 HORIZONTAL DIP-8 D2PAK-5 D2PAK-5 SO-14 SO-14 Shipping 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 50 Units/Rail 750 Tape & Reel 55 Units/Rail 2500 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
MARKING DIAGRAMS
TO-220-5 T SUFFIX CASE 314D TO-220-5 TVA SUFFIX CASE 314K TO-220-5 THA SUFFIX CASE 314A DIP-8 N SUFFIX CASE 626 8
CS8120
D2PAK-5 DP SUFFIX CASE 936F 14
SO-14 D SUFFIX CASE 751A
CS8120 CS8120
AWL YYWW
CS8120 AWLYWW CS8120 AWLYWW CS8120 AWLYWW
AWLYWW 1
AWLYWW
1 1
1
1
1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week
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CS8120
PACKAGE DIMENSIONS
TO-220-5 T SUFFIX CASE 314D-04 ISSUE E
-T- -Q- B C E
SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E G H J K L Q U INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.067 BSC 0.087 0.112 0.015 0.025 0.990 1.045 0.320 0.365 0.140 0.153 0.105 0.117 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 1.702 BSC 2.210 2.845 0.381 0.635 25.146 26.543 8.128 9.271 3.556 3.886 2.667 2.972
U K
12345
A L
G D
5 PL
J H
M
0.356 (0.014)
M
TQ
TO-220-5 TVA SUFFIX CASE 314K-01 ISSUE O
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D, INCLUDING PROTRUSION, SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM A B C D E F G J K L M Q R S U W INCHES MIN MAX 0.560 0.590 0.385 0.415 0.160 0.190 0.027 0.037 0.045 0.055 0.530 0.545 0.067 BSC 0.014 0.022 0.785 0.800 0.321 0.337 0.063 0.078 0.146 0.156 0.271 0.321 0.146 0.196 0.460 0.475 5_ MILLIMETERS MIN MAX 14.22 14.99 9.78 10.54 4.06 4.83 0.69 0.94 1.14 1.40 13.46 13.84 1.70 BSC 0.36 0.56 19.94 20.32 8.15 8.56 1.60 1.98 3.71 3.96 6.88 8.15 3.71 4.98 11.68 12.07 5_
-T- B -Q- W U
12345
SEATING PLANE
C E
A L M G J S R
F K
D
5 PL M
0.356 (0.014)
TQ
M
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CS8120
PACKAGE DIMENSIONS
TO-220-5 THA SUFFIX CASE 314A-03 ISSUE E
SEATING PLANE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. INCHES MIN MAX 0.572 0.613 0.390 0.415 0.170 0.180 0.025 0.038 0.048 0.055 0.570 0.585 0.067 BSC 0.015 0.025 0.730 0.745 0.320 0.365 0.140 0.153 0.210 0.260 0.468 0.505 MILLIMETERS MIN MAX 14.529 15.570 9.906 10.541 4.318 4.572 0.635 0.965 1.219 1.397 14.478 14.859 1.702 BSC 0.381 0.635 18.542 18.923 8.128 9.271 3.556 3.886 5.334 6.604 11.888 12.827
-T- B -P-
OPTIONAL CHAMFER
C E
Q
U
A L
F
K
G
5X
5X
J
D 0.014 (0.356)
M
S TP
M
DIM A B C D E F G J K L Q S U
D2PAK-5 DP SUFFIX CASE 936AC-01 ISSUE O
For D2PAK Outline and Dimensions - Contact Factory
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CS8120
PACKAGE DIMENSIONS
SO-14 D SUFFIX CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
G C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
DIP-8 N SUFFIX CASE 626-05 ISSUE L
8 5
-B-
1 4
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
F
NOTE 2
-A- L
C -T-
SEATING PLANE
J N D K
M
M TA
M
H
G 0.13 (0.005) B
M
PACKAGE THERMAL DATA Parameter RqJC RqJA Typical Typical TO-220-5 3.1 50 D2PAK-5 3.1 10-50* DIP-8 52 100 SO-14 30 125 Unit C/W C/W
* Depending on thermal properties of substrate. RqJA = RqJC + RqCA
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CS8120
SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC).
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Phone: 81-3-5773-3850 ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative.
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CS8120/D

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